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Si413 3 Si4 123 /2 2/13 /1 2
D U A L -B A N D R F S Y N T H E S I Z E R WI T H I N T E G R A T E D V C O S F O R WI R E L E S S C O M M U N I C A T I O N S
Features
!
" "
RF1: 900 MHz to 1.8 GHz RF2: 750 MHz to 1.5 GHz IF: 62.5 MHz to 1000 MHz
! ! ! !
! ! !
IF Synthesizer
"
Integrated VCOs, Loop Filters, ! Varactors, and Resonators Minimal (2) External Components Required
S
Dual-Band RF Synthesizers
!
Low Phase Noise Programmable Power Down Modes 1 A Standby Current 18 mA Typical Supply Current 2.7 V to 3.6 V Operation Packages: 24-Pin TSSOP, 28-Lead MLP
i4
13
Ordering Information: See page 31.
Applications
! !
Dual-Band Communications Digital Cellular Telephones GSM, DCS1800, PCS1900
! ! !
Digital Cordless Phones Analog Cordless Phones Wireless LAN and WAN
3-
Pin Assignments
B
T
SI4133-BT
SCLK SDA TA GNDR RFLD RFLC GNDR RFLB RFLA GNDR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SENB V DDI IFOUT GNDI IFLB IFLA GNDD V DDD GNDD XIN PWDNB A UXOUT
Description
The SI4133 is a monolithic integrated circuit that performs both IF and dualband RF synthesis for wireless communications applications. The SI4133 includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and power-down settings are programmable through a three-wire serial interface.
Functional Block Diagram
GNDR RFOUT V DDR
X IN
R eference A m plifier P ow er D ow n C ontrol
/R
P hase D etector R F1
R FLA R FLB
PW DNB
/N /R
R FO UT
GNDR
SI4133-BM
SDA TA SCLK SENB IFOUT GNDI V DDI
S D AT A S C LK S E NB
S erial Interface 22-bit D ata R egister
P hase D etector R F2
R FLC R FLD
GNDR
28 1 2 3 4 5 6 7 8
GNDR
27
26
25
24
23
22 21 20 19 18 17 16 15
GNDI IFLB IFLA GNDD V DDD GNDD XIN
/N
RFLD
A U XO U T
Test Mux
/R
P hase D etector IF
RFLC
IFD IV
IFO U T
GNDR RFLB RFLA GNDR
/N
IFLA IFLB
9
GNDR
10
RFOUT
11
V DDR
12
A UXOUT
13
PWDNB
14
GNDD
Patents pending
Rev. 1.1 3/01 Copyright (c) 2001 by Silicon Laboratories SI4133-DS11
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
S i4 13 3
2
Rev. 1.1
SI4133 TA B L E O F CON T E N T S
Section Page
4 16 16 16 17 17 18 18 19 19 19 20 21 27 29 31 31 32 33 34
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the VCO Center Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extended Frequency Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-Tuning Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Output (AUXOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI4133-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: SI4133-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SI4133 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: SI4133-BT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline: SI4133-BM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. 1.1
3
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Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Symbol TA VDD V (VDDR - VDDD), (VDDI - VDDD) Test Condition Min -40 2.7 -0.3 Typ 25 3.0 -- Max 85 3.6 0.3 Unit C V V
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter DC Supply Voltage Input Current3 Input Voltage3 Storage Temperature Range Symbol VDD IIN VIN TSTG Value -0.5 to 4.0 10 -0.3 to VDD+0.3 -55 to 150 Unit V mA V
o
C
Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This device is a high performance RF integrated circuit with an ESD rating of < 2 kV. Handling and assembly of this device should only be done at ESD-protected workstations. 3. For signals SCLK, SDATA, SENB, PWDNB and XIN.
4
Rev. 1.1
SI4133
Table 3. DC Characteristics
(VDD = 2.7 to 3.6 V, TA = -40 to 85C) Parameter Total Supply Current
1
Symbol
Test Condition RF1 and IF operating
Min -- -- -- --
Typ 18 10 9 8 1 -- -- -- -- -- --
Max 27 16 16 13 -- -- 0.3 VDD 10 10 -- 0.4
Unit mA mA mA mA A V V A A V V
RF1 Mode Supply Current1 RF2 Mode Supply Current1 IF Mode Supply Current1 Standby Current High Level Input Voltage2 Low Level Input Voltage2 High Level Input Current2 Low Level Input Current2 High Level Output Voltage3 Low Level Output Voltage3 VIH VIL IIH IIL VOH VOL VIH = 3.6 V, VDD = 3.6 V VIL = 0 V, VDD= 3.6 V IOH = -500 A IOH = 500 A PWDNB = 0
-- 0.7 VDD -- -10 -10 VDD-0.4 --
Notes: 1. RF1 = 1.6 GHz, RF2 = 1.1 GHz, IFOUT = 550 MHz, LPWR = 0 2. For signals SCLK, SDATA, SENB, and PWDNB. 3. For signal AUXOUT.
Rev. 1.1
5
S i4 13 3
Table 4. Serial Interface Timing
(VDD = 2.7 to 3.6 V, TA = -40 to 85C) Parameter1 SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time SDATA Setup Time to SCLK2 SDATA Hold Time from SCLK2 SENB to SCLK Delay Time
2
Symbol tclk tr tf th tl tsu thold ten1 ten2 ten3 tw
Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2
Min 40 -- -- 10 10 5 0 10 12 12 10
Typ -- -- -- -- -- -- -- -- -- -- --
Max -- 50 50 -- -- -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns
SCLK to SENB Delay Time2 SENB to SCLK Delay Time2 SENB Pulse Width
Notes: 1. All timing is referenced to the 50% level of the waveforms unless otherwise noted. 2. Timing is not referenced to 50% level of the waveform. See Figure 2.
tr
80%
tf
S CLK
50% 20%
th
t clk
tl
Figure 1. SCLK Timing Diagram
6
Rev. 1.1
SI4133
ts u thold
S CLK
S DA TA
D17
D16
D15
A1
A0 ten3 ten2
ten1
S E NB
tw
Figure 2. Serial Interface Timing Diagram
First bit c loc ked in
Las t bit c loc ked in
DDDDDDDDD 17 16 15 14 13 12 11 10 9
D 8
D 7
D 6
DD 54
D 3
D 2
D 1
D 0
A 3
A 2
A 1
A 0
data field
addres s field
Figure 3. Serial Word Format
Rev. 1.1
7
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Table 5. RF and IF Synthesizer Characteristics
(VDD = 2.7 to 3.6 V, TA = -40 to 85C)
Parameter1 XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency RF1 VCO Center Frequency Range RF1 VCO Tuning Range2 RF2 VCO Center Frequency Range RF Tuning Range from fCEN IF VCO Center Frequency Range IFOUT Tuning Range IFOUT Tuning Range from fCEN RF1 VCO Pushing RF2 VCO Pushing IF VCO Pushing RF1 VCO Pulling RF2 VCO Pulling IF VCO Pulling RF1 Phase Noise RF1 Integrated Phase Error RF2 Phase Noise RF2 Integrated Phase Error IF Phase Noise IF Integrated Phase Error
Symbol fREF VREF f fCEN
Test Condition
Min 2 0.5
Typ -- -- -- -- -- -- -- -- -- -- 500 400 300 900 300 100 -132 0.9 -134 0.7 -117 0.4
Max 26 VDD +0.3 V 1.0 1720 2050 1429 5 952 1000 5 -- -- -- -- -- -- -- -- -- -- -- --
Unit MHz VP-P MHz MHz MHz MHz % MHz MHz % kHz/V kHz/V kHz/V MHz kHz kHz dBc/Hz degrees rms dBc/Hz degrees rms dBc/Hz degrees rms
f = fREF/R
0.010 947
Extended frequency operation fCEN Note: LEXT 10% fCEN with IFDIV Note: LEXT 10% Open loop
1850 789 -5 526 62.5 -5 -- -- --
VSWR = 2:1, all phases, open loop
-- -- --
1 MHz offset 10 Hz to 100 kHz 1 MHz offset 10 Hz to 100 kHz 100 kHz offset 100 Hz to 100 kHz
-- -- -- -- -- --
Notes: 1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. Extended frequency operation only. VDD 3.0 V, MLP only, VCO Tuning Range fixed by directly shorting the RFLA and RFLB pins. See Application Note 41 for more details on the SI4133 extended frequency operation. 3. From power up request (PWDNB or SENB during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From power down request (PWDNB, or SENB during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN.
8
Rev. 1.1
SI4133
Table 5. RF and IF Synthesizer Characteristics (Continued)
(VDD = 2.7 to 3.6 V, TA = -40 to 85C)
Parameter1 RF1 Harmonic Suppression RF2 Harmonic Suppression IF Harmonic Suppression RFOUT Power Level RFOUT Power Level
2
Symbol
Test Condition Second Harmonic
Min -- -- --
Typ -26 -26 -26 -3 -7
Max -20 -20 -20 1 1
Unit dBc dBc dBc dBm dBm
ZL = 50 ZL = 50 , RF1 active, Extended frequency operation ZL = 50 Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz
-8 -14
IFOUT Power Level RF1 Output Reference Spurs
-8 -- -- -- -- -- -- -- --
-4 -65 -71 -75 -65 -71 -75 40/f --
0 -- -- -- -- -- -- 50/f 100
dBm dBc dBc dBc dBc dBc dBc
RF2 Output Reference Spurs
Offset = 200 kHz Offset = 400 kHz Offset = 600 kHz
Power Up Request to Synthesizer Ready3 Time Power Down Request to Synthesizer Off4 Time
tpup tpdn
Figures 4, 5 Figures 4, 5
ns
Notes: 1. f = 200 kHz, RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. Extended frequency operation only. VDD 3.0 V, MLP only, VCO Tuning Range fixed by directly shorting the RFLA and RFLB pins. See Application Note 41 for more details on the SI4133 extended frequency operation. 3. From power up request (PWDNB or SENB during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). 4. From power down request (PWDNB, or SENB during a write of 0 to bits PDIB and PDRB in Register 2) to supply current equal to IPWDN.
Rev. 1.1
9
S i4 13 3
RF and IF sy nthes iz ers settled to w ithin 0.1 ppm f requency error.
RF and IF synthes izers settled to w ithin 0.1 ppm f requenc y error.
IT I PW D N
tpup
tpdn
IT IPW D N
tpup
tpdn
S E NB
P W DNB
S DA TA
PD IB = 1 PD R B = 1
PD IB = 0 PD R B = 0
Figure 4. Software Power Management Timing Diagram
Figure 5. Hardware Power Management Timing Diagram
10
Rev. 1.1
SI4133
TRACE A: Ch1 FM Main Time A Marker 1.424 kHz
174.04471
us
711.00
Hz
Real
160 Hz /div
176 Hz Start: 0 s Stop: 399.6003996 us
Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency
Rev. 1.1
11
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-60
-70
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140 2 10
10
3
10 Offset Frequency (Hz)
4
10
5
10
6
Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency
Figure 8. Typical RF1 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency
12
Rev. 1.1
SI4133
-60
-70
-80
Phase Noise (dBc/Hz)
-90
-100
-110
-120
-130
-140 2 10
10
3
10 Offset Frequency (Hz)
4
10
5
10
6
Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency
Figure 10. Typical RF2 Spurious Response at 1.2 GHz with 200 kHz Phase Detector Update Frequency
Rev. 1.1
13
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-70
-80
-90
Phase Noise (dBc/Hz)
-100
-110
-120
-130
-140
-150 2 10
10
3
10 Offset Frequency (Hz)
4
10
5
10
6
Figure 11. Typical IF Phase Noise at 550 MHz with 200 kHz Phase Detector Update Frequency
Figure 12. IF Spurious Response at 550 MHz with 200 kHz Phase Detector Update Frequency
14
Rev. 1.1
SI4133
VDD
S i4133 -B T
F ro m S ys te m C o n tro lle r
1 2 3 4 5
SCLK S D ATA GNDR RFLD RFLC
SENB VDDI IFO U T GNDI IFL B IFL A GNDD VDDD GNDD X IN PW DNB AU X O U T
24 23
30 * 0 .0 2 2 F 10nH 5 6 0 pF IFO U T
22 21 20 19 18 17 16
P rinte d Tra c e Ind uc tors
6
P rinte d Tra c e Ind uc tor o r C h ip In d uc to r
GNDR
7 8 9 10
RFLB RFLA GNDR GNDR
V DD
0.022 F
5 6 0 pF
15 14 13
E x te rna l C loc k PW DNB AU X O U T
5 6 0 pF RFOUT
2nH
11
RFOUT
0.022 F
V DD
12
VDDR
* Ad d 3 0 s e rie s re s is ta nc e if u s ing IF ou tpu t divid e v a lue s 2 , 4 , o r 8 .
Figure 13. Typical Application Circuit: SI4133-BT
VDD
30 *
F ro m S ys te m C o n tro lle r
28 27 26 25 24
0.022 F 10nH 560pF
IFO U T
23 22
SEN B
SD ATA
IF OUT
G NDR
SC LK
G NDI
V DDI
1 2 3
GNDR RFLD RFLC GNDR RFLB RFLA
GNDI IFL B IFL A
21 20 19 18 17 16 15
P rinte d Tra c e Ind u c tor o r C h ip In d uc tor
P rinte d Tra c e Ind u c tors
4 5 6 7
S i4133 -B M
GNDD VDDD GNDD
V DD
0.022 F 560pF
AUXOUT
PWD NB
RFOUT
GNDR
X IN
E x te rna l C loc k
GNDR
GNDR
8
9
10
11
12
13
14
V DD 0.022 F
AUXOUT PW DNB
GNDD
VDDR
2nH
560pF
RFO UT
* Ad d 3 0 s e rie s re s is ta nc e if us in g IF ou tp ut d iv id e va lu e s 2 , 4 , o r 8 .
Figure 14. Typical Application Circuit: SI4133-BM
Rev. 1.1
15
S i4 13 3
Functional Description
The SI4133 is a monolithic integrated circuit that performs IF and dual-band RF synthesis for wireless communications applications. This integrated circuit (IC), with minimal external components, completes the frequency synthesis function necessary for RF communications systems. The SI4133 has three complete phase-locked loops (PLLs) with integrated voltage-controlled oscillators (VCOs). The low phase noise of the VCOs makes the SI4133 suitable for use in demanding wireless communications applications. Phase detectors, loop filters, and reference and output frequency dividers are integrated. The IC is programmed through a three-wire serial interface. Two PLLs are provided for dual-band RF synthesis. These RF PLLs are multiplexed so that only one PLL is active at a given time (as determined by the setting of an internal register). The active PLL is the last one written. The center frequency of the VCO in each PLL is set by the value of an external inductance. Inaccuracies in these inductances are compensated for by the selftuning algorithm. The algorithm is run following powerup or following a change in the programmed output frequency. Each RF PLL, when active, can adjust the RF output frequency by 5% of its VCO's center frequency. Because the two VCOs can be set to have widely separated center frequencies, the RF output can be programmed to service two widely separated frequency bands by simply programming the corresponding NDivider. One RF VCO is optimized to have its center frequency set between 947 MHz and 1.72 GHz, while the second RF VCO is optimized to have its center frequency set between 789 MHz and 1.429 GHz. One PLL is provided for IF frequency synthesis. The center frequency of this circuit's VCO is set by connection of an external inductance. The PLL can adjust the IF output frequency by 5% of the VCO center frequency. Inaccuracies in the value of the external inductance are compensated for by the SI4133's proprietary self-tuning algorithm. This algorithm is initiated each time the PLL is powered-up (by either the PWDNB pin or by software) and/or each time a new output frequency is programmed. The IF VCO can have its center frequency set as low as 526 MHz and as high as 952 MHz. An IF output divider is provided to divide down the IF output frequencies, if needed. The divider is programmable, capable of dividing by 1, 2, 4, or 8. The unique PLL architecture used in the SI4133 produces settling (lock) times that are comparable in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often associated with those designs.
Serial Interface
A timing diagram for the serial interface is shown in Figure 2 on page 7. Figure 3 on page 7 shows the format of the serial word. The SI4133 is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. When the serial interface is enabled (i.e., when SENB is low) data and address bits on the SDATA pin are clocked into an internal shift register on the rising edge of SCLK. Data in the shift register is then transferred on the rising edge of SENB into the internal data register addressed in the address field. The serial interface is disabled when SENB is high. Table 12 on page 21 summarizes the data register functions and addresses. The internal shift register will ignore any leading bits before the 22 required bits.
Setting the VCO Center Frequencies
The PLLs can adjust the IF and RF output frequencies 5% of the center frequencies of their VCOs. Each center frequency is established by the value of an external inductance connected to the respective VCO. Manufacturing tolerances of 10% for the external inductances are acceptable. The SI4133 will compensate for inaccuracies in each inductance by executing a self-tuning algorithm following PLL powerup or following a change in the programmed output frequency. Because the total tank inductance is in the low nH range, the inductance of the package needs to be considered in determining the correct external inductance. The total inductance (LTOT) presented to each VCO is the sum of the external inductance (LEXT) and the package inductance (LPKG). Each VCO has a nominal capacitance (CNOM) in parallel with the total inductance, and the center frequency is as follows:
16
Rev. 1.1
SI4133
1 f CEN = --------------------------------------------2 L TOT C NOM
or
1 fCEN = ---------------------------------------------------------------------2 ( L PKG + L EXT ) CNOM
Tables 6 and 7 summarize the characteristics of each VCO.
Table 6. SI4133-BT VCO Characteristics
VCO fCEN Range (MHz) Min Max CNOM (pF) LPKG (nH) LEXT Range (nH) Min Max
1145 MHz. The center frequency should be defined as midway between the two extremes, or 1132.5 MHz. The PLL will be able to adjust the VCO output frequency 5% of the center frequency, or 56.6 MHz of 1132.5 MHz (i.e., from approximately 1076 MHz to 1189 MHz). The RF2 VCO has a CNOM of 4.8 pF. A 4.1 nH inductance (correct to two digits) in parallel with this capacitance will yield the desired center frequency. An external inductance of 1.8 nH should be connected between RFLC and RFLD as shown in Figure 15. This, in addition to 2.3 nH of package inductance, will present the correct total inductance to the VCO. In manufacturing, the external inductance can vary 10% of its nominal value and the SI4133 will correct for the variation with the self-tuning algorithm. For more information on designing the external trace inductors, refer to Application Note 31.
RF1 RF2 IF
947 789 526
1720 1429 952
4.3 4.8 6.5
2.0 2.3 2.1
0.0 0.3 2.2
4.6 6.2 12.0
Extended Frequency Operation
The SI4133 may operate at an extended frequency range of 1850 MHz to 2050 MHz by connecting the RFLA and RFLB pins directly. For information on configuring the SI4133 for extended frequency operation, refer to Application Note 41.
Table 7. SI4133-BM VCO Characteristics
VCO fCEN Range (MHz) Min Max CNOM (pF) LPKG (nH) LEXT Range (nH) Min Max
Self-Tuning Algorithm
The self-tuning algorithm is initiated immediately following power-up of a PLL or, if the PLL is already powered, following a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its free-running frequency is near the desired output frequency. In doing so, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the VCO. It will also reduce the frequency error for which the PLL must correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations. The SI4133's self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with temperature coefficients around 150 ppm/oC, the PLL will be able to maintain lock for changes in temperature of approximately 30 oC.
RF1 RF2 IF
947 789 526
1720 1429 952
4.3 4.8 6.5
1.5 1.5 1.6
0.5 1.1 2.7
5.1 7.0 12.5
L PK G 2 L EXT
L PK G 2
Figure 15. External Inductance Connection
As a design example, suppose the goal is to synthesize frequencies in a 25 MHz band between 1120 MHz and
Rev. 1.1
17
S i4 13 3
Applications where the PLL is regularly powered-down or the frequency is periodically reprogrammed minimize or eliminate the potential effects of temperature drift because the VCO is re-tuned in either case. In applications where the ambient temperature can drift substantially after self-tuning, it may be necessary to monitor the lock-detect bar (LDETB) signal on the AUXOUT pin to determine whether a PLL is about to run out of locking capability. (See "Auxiliary Output (AUXOUT)" for how to select LDETB.) The LDETB signal will be low after self-tuning has completed but will rise when either the IF or RF PLL nears the limit of its compensation range. (LDETB will also be high when either PLL is executing the self-tuning algorithm.) The output frequency will still be locked when LDETB goes high, but the PLL will eventually lose lock if the temperature continues to drift in the same direction. Therefore, if LDETB goes high both the IF and RF PLLs should promptly be re-tuned by initiating the self-tuning algorithm.
PLL Loop Dynamics
The transient response for each PLL is determined by its phase detector update rate f (equal to fREF/R) and the phase detector gain programmed for each RF1, RF2, or IF synthesizer. (See Register 1.) Four different settings for the phase detector gain are available for each PLL. The highest gain is programmed by setting the two phase detector gain bits to 00, and the lowest by setting the bits to 11. The values of the available gains, relative to the highest gain, are as follows:
Table 8. Gain Values (Register 1)
KP Bits 00 01 10 11 Relative P.D. Gain 1 1/2 1/4 1/8
Output Frequencies
The IF and RF output frequencies are set by programming the R- and N-Divider registers. Each PLL has its own R and N registers so that each can be programmed independently. Programming either the Ror N-Divider register for RF1 or RF2 automatically selects the associated output. The reference frequency on the XIN pin is divided by R and this signal is input to the PLL's phase detector. The other input to the phase detector is the PLL's VCO output frequency divided by N. The PLL acts to make these frequencies equal. That is, after an initial transient
f OUT fREF ----------- = ----------N R
The gain value bits can be automatically set by setting the Auto KP bit (bit 2) in the Main Configuration register to 1. In setting this bit, the gain values will be optimized for a given value of N. In general, a higher phase detector gain will decrease in-band phase noise and increase the speed of the PLL transient until the point at which stability begins to be compromised. The optimal gain depends on N. Table 9 lists recommended settings for different values of N. These are the settings used when the Auto KP bit is set.
Table 9. Optimal KP Settings
N 2047 RF1 KP1<1:0> 00 00 00 01 10 11 RF2 KP2<3:2> 00 00 01 10 11 11 IF KPI<5:4> 00 01 10 11 11 11
or
fOUT N = --- fREF R
2048 to 4095 4096 to 8191 8192 to 16383 16384 to 32767 32768
The R values are set by programming the RF1 RDivider register (Register 6), the RF2 R-Divider register (Register 7) and the IF R-Divider register (Register 8). The N values are set by programming the RF1 NDivider register (Register 3), the RF2 N-Divider register (Register 4), and the IF N-Divider register (Register 5). Each N-Divider is implemented as a conventional high speed divider. That is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. However, the control of these sub-circuits is handled automatically. Only the appropriate N value should be programmed.
The VCO gain and loop filter characteristics are not programmable. The settling time for the PLL is directly proportional to its phase detector update period T (T equals 1/f). A typical transient response is shown in Figure 6 on page 11. During the first 13 update periods the SI4133 executes the self-tuning algorithm. Thereafter the PLL
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SI4133
controls the output frequency. Because of the unique architecture of the SI4133 PLLs, the time required to settle the output frequency to 0.1 ppm error is only about 25 update periods. Thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled--including time for self-tuning--is around 40 update periods.
Note: The settling time analysis holds for RF1 f 500 kHz. For RF1 f > 500 kHz, the settling time is larger.
560 pF IFOUT L MATCH 50
Figure 16. IF Frequencies > 500 MHz
For frequencies less than 500 MHz, the IF output buffer can directly drive a 200 resistive load or higher. For resistive loads greater than 500 (f < 500 MHz) the LPWR bit can be set to reduce the power consumed by the IF output buffer. See Figure 17 below.
>500 pF IFOUT
RF and IF Outputs
The RFOUT and IFOUT pins are driven by amplifiers that buffer the RF VCOs and IF VCO, respectively. The RF output amplifier receives its input from either the RF1 or RF2 VCO, depending upon which R- or NDivider register was last written. For example, programming the N-Divider register for RF1 automatically selects the RF1 VCO output. Figures 13 and 14 show application diagrams for the SI4133. The RF output signal must be AC coupled to its load through a capacitor. An external inductance between the RFOUT pin and the AC coupling capacitor is required as part of an output matching network to maximize power delivered to the load. This 2 nH inductance may be realized with a PC board trace. The network is made to provide an adequate match to an external 50 load for both the RF1 and RF2 frequency bands. The matching network also filters the output signal to reduce harmonic distortion. The IFOUT pin must also be AC coupled to its load through a capacitor. The IF output level is dependent upon the load. Figure 18 on page 20 displays the output level versus load resistance for a variety of output frequencies. For resistive loads greater than 500 the output level saturates and the bias currents in the IF output amplifier are higher than they need to be. The LPWR bit in the Main Configuration register (Register 0) can be set to 1 to reduce the bias currents and therefore reduce the power dissipated by the IF amplifier. For loads less than 500 , LPWR should be set to 0 to maximize the output level. For IF frequencies greater than 500 MHz, a matching network is required in order to drive a 50 load. See Figure 16 below. The value of LMATCH can be determined from Table 10.
>200
Figure 17. IF Frequencies < 500 MHz
Reference Frequency Amplifier
The SI4133 provides a reference frequency amplifier. If the driving signal has CMOS levels it can be connected directly to the XIN pin. Otherwise, the reference frequency signal should be AC coupled to the XIN pin through a 560 pF capacitor.
Power Down Modes
Table 11 summarizes the power down functionality. The SI4133 can be powered down by taking the PWDNB pin low or by setting bits in the Power Down register (Register 2). When the PWDNB pin is low, the SI4133 will be powered down regardless of the Power Down register settings. When the PWDNB pin is high, power management is under control of the Power Down register bits. The IF and RF sections of the SI4133 circuitry can be individually powered down by setting the Power Down register bits PDIB and PDRB low, respectively. Note that the reference frequency amplifier will also be powered up if either the PDRB and PDIB bits are high. Also, setting the AUTOPDB bit to 1 in the Main Configuration register (Register 0) is equivalent to setting both bits in the Power Down register to 1. The serial interface remains available and can be written in all power down modes.
Table 10. LMATCH Values
Frequency 500-600 MHz 600-800 MHz 800 MHz-1 GHz LMATCH 40 nH 27 nH 18 nH
Rev. 1.1
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S i4 13 3
Auxiliary Output (AUXOUT)
The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). The LDETB signal can be selected by setting the AUXSEL bits to 11. This signal can be used to indicate that the IF or RF PLL is about to lose lock due to excessive ambient temperature drift and should be re-tuned.
Table 11. Power Down Configuration
PWDNB Pin PWDNB = 0 AUTOPDB X 0 0 PWDNB = 1 0 0 1 PDIB X 0 0 1 1 x PDRB X 0 1 0 1 x IF Circuitry OFF OFF OFF ON ON ON RF Circuitry OFF OFF ON OFF ON ON
450
400
350 LPWR=1 LPWR=0 300 Output Voltage (mVrms)
250
200
150
100
50
0 0 200 400 600 Load Resistance () 800 1000 1200
Figure 18. Typical IF Output Voltage vs. Load Resistance at 550 MHz
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Rev. 1.1
SI4133
Control Registers
Table 12. Register Summary
Register Name Bit Bit Bit Bit 17 16 15 14 Bit 13 Bit 12 Bit 11 Bit Bit Bit Bit Bit 10 9 8 7 6 Bit 5
LPWR
Bit 4
Bit 3
Bit 2
Bit 1
RF PWR
Bit 0
0 1 2 3 4 5 6 7 8 9 . . . 15
Main Configuration Phase Detector Gain Power Down
0 0 0
0 0 0
0 0 0
0 0 0
AUXSEL [1:0]
IFDIV
[1:0]
0 0 0
0 0 0
0 0 0
0 0 0
0
AUTO AUTO PDB KP
0
0 0
0 0
0 0
0 0
KPI[1:0] 0 0
KP2[1:0] 0 0
KP1[1:0]
PDIB PDRB
RF1
N-Divider
NRF1[17:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NRF2[16:0] NIF[15:0] RRF1[12:0] RRF2[12:0] RIF[12:0]
RF2
N-Divider IF N-Divider
RF1
R-Divider
RF2
R-Divider IF R-Divider
Reserved
Reserved
Note: Registers 9-15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed here is reserved and should not be written.
Rev. 1.1
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Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 AUXSEL
[1:0]
D8 0
D7 0
D6 0
D5
LPWR
D4 0
D3
AUTO PDB
D2
AUTO KP
D1
RF PWR
D0 0
IFDIV
[1:0]
0
Bit 17:14 13:12
Name Reserved AUXSEL[1:0] Program to zero.
Function
Auxiliary Output Pin Definition. 00 = Reserved. 01 = Force output low. 10 = Reserved. 11 = Lock Detect--LDETB. IF Output Divider. 00 = IFOUT = IFVCO Frequency 01 = IFOUT = IFVCO Frequency/2 10 = IFOUT = IFVCO Frequency/4 11 = IFOUT = IFVCO Frequency/8 Program to zero. Output Power-Level Settings for IF Synthesizer Circuit. 0 = RLOAD < 500 --normal power mode. 1 = RLOAD 500 --low power mode. Program to zero. Auto Power Down. 0 = Software powerdown is controlled by Register 2. 1 = Equivalent to setting all bits in Register 2 = 1. Auto KP Setting. 0 = KPs are controlled by Register 1. 1 = KPs are set according to Table 9 on page 18. Program to zero. (Used for extended frequency operation. See AN41 for more information.) Program to zero.
11:10
IFDIV[1:0]
9:6 5
Reserved LPWR
4 3
Reserved AUTOPDB
2
AUTOKP
1 0
RFPWR Reserved
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Rev. 1.1
SI4133
Register 1. Phase Detector Gain Address Field (A[3:0]) = 0001 Bit Name Bit 17:6 5:4 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 0 0 0 0 0 D9 0 D8 0 D7 0 D6 0 D5 D4 D3 D2 D1 D0
KPI[1:0]
KP2[1:0]
KP1[1:0]
Name Reserved KPI[1:0] Program to zero.
Function
IF Phase Detector Gain Constant.* N Value KPI <2048 = 00 2048-4095 = 01 4096-8191 = 10 >8191 = 11 RF2 Phase Detector Gain Constant.* N Value KP2 <4096 = 00 4096-8191 = 01 8192-16383 = 10 >16383 = 11 RF1 Phase Detector Gain Constant.* N Value KP1 <8192 = 00 8192-16383 = 01 16384-32767 = 10 >32767 = 11
3:2
KP2[1:0]
1:0
KP1[1:0]
*Note: When AUTOKP = 1, these bits do not need to be programmed. When AUTOKP = 0, use these recommended values for programming Phase Detector Gain.
Rev. 1.1
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S i4 13 3
Register 2. Power Down Address Field (A[3:0]) = 0010 Bit Name Bit 17:2 1 D17 D16 D15 D14 D13 D12 D11 D10 D9 0 0 0 0 Name Reserved PDIB Program to 0. Power Down IF Synthesizer. 0 = IF synthesizer powered down. 1 = IF synthesizer on. Power Down RF Synthesizer. 0 = RF synthesizer powered down. 1 = RF synthesizer on. 0 0 0 0 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 D0
PDIB PDRB
Function
0
PDRB
Note: Enabling any PLL with PDIB or PDRB will automatically power on the reference amplifier.
Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011 Bit Name Bit 17:0 Name NRF1[17:0] N-Divider for RF1 Synthesizer. D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF1[17:0] Function
Register 4. RF2 N-Divider Address Field = A[3:0] = 0100 Bit Name Bit 17 16:0 D17 D16 D15 D14 D13 D12 D11 D10 0 Name Reserved NRF2[16:0] Program to 0. N-Divider for RF2 Synthesizer. D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NRF2[16:0] Function
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Rev. 1.1
SI4133
Register 5. IF N-Divider Address Field (A[3:0]) = 0101 Bit Name Bit 17:16 15:0 D17 D16 D15 D14 D13 D12 D11 D10 0 0 Name Reserved NIF[15:0] Program to zero. N-Divider for IF Synthesizer. D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NIF[15:0] Function
Register 6. RF1 R-Divider Address Field (A[3:0]) = 0110 Bit Name D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Name 17:13 12:0 Reserved RRF1[12:0] Program to zero. R-Divider for RF1 Synthesizer. RRF1 can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RRF1[12:0] Function
Register 7. RF2 R-Divider Address Field (A[3:0]) = 0111 Bit Name Bit 17:13 12:0 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Name Reserved RRF2[12:0] Program to zero. R-Divider for RF2 Synthesizer. RRF2 can be any value from 7 to 8189 if KP2 = 00 8 to 8189 if KP2 = 01 10 to 8189 if KP2 = 10 14 to 8189 if KP2 = 11 0 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RRF2[12:0] Function
Rev. 1.1
25
S i4 13 3
Register 8. IF R-Divider Address Field (A[3:0]) = 1000 Bit Name Bit 17:13 12:0 D17 D16 D15 D14 D13 D12 D11 D10 0 0 0 Name Reserved RIF[12:0] Program to zero. R-Divider for IF Synthesizer. RIF can be any value from 7 to 8189 if KP1 = 00 8 to 8189 if KP1 = 01 10 to 8189 if KP1 = 10 14 to 8189 if KP1 = 11 0 0 D9 D8 D7 D6 RIF[12:0] Function D5 D4 D3 D2 D1 D0
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Rev. 1.1
SI4133
Pin Descriptions: SI4133-BT
SCLK SDA TA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT V DDR
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
SENB V DDI IFOUT GNDI IFLB IFLA GNDD V DDD GNDD XIN PWDNB A UXOUT
Pin Number(s) Name 1 2 3, 6, 9, 10 4, 5 7, 8 11 12 13 14 15 16, 18 17 19, 20 21 22 23 24 SCLK SDATA GNDR RFLC, RFLD RFLA, RFLB RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD IFLA, IFLB GNDI IFOUT VDDI SENB
Description Serial clock input Serial data input Common ground for RF analog circuitry Pins for inductor connection to RF2 VCO Pins for inductor connection to RF1 VCO Radio frequency (RF) output of the selected RF VCO Supply voltage for the RF analog circuitry Auxiliary output Power down input pin Reference frequency amplifier input Common ground for digital circuitry Supply voltage for digital circuitry Pins for inductor connection to IF VCO Common ground for IF analog circuitry Intermediate frequency (IF) output of the IF VCO Supply voltage for IF analog circuitry Enable serial port input
Rev. 1.1
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S i4 13 3
Table 13. Pin Descriptions for SI4133 Derivatives--TSSOP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SI4133 SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB Si4123 SCLK SDATA GNDR GNDR GNDR GNDR RFLB RFLA GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB Si4122 SCLK SDATA GNDR RFLD RFLC GNDR GNDR GNDR GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB Si4113 SCLK SDATA GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR RFOUT VDDR AUXOUT PWDNB XIN GNDD VDDD GNDD GNDD GNDD GNDD GNDD VDDD SENB Si4112 SCLK SDATA GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD VDDD AUXOUT PWDNB XIN GNDD VDDD GNDD IFLA IFLB GNDI IFOUT VDDI SENB
28
Rev. 1.1
SI4133
Pin Descriptions: SI4133-BM
SDA TA GNDR SENB IFOUT SCLK V DDI GNDI
28
GNDR RFLD RFLC GNDR RFLB RFLA GNDR
27
26
25
24
23
22 21 20 19 18 17 16 15
GNDI IFLB IFLA GNDD V DDD GNDD XIN
1 2 3 4 5 6 7 8
GNDR
9
GNDR
10
RFOUT
11
V DDR
12
A UXOUT
13
PWDNB
14
GNDD
Pin Number(s) Name 1, 4, 7-9, 28 2, 3 5,6 10 11 12 13 14, 16, 18 15 17 19, 20 21, 22 23 24 25 26 27 GNDR RFLC, RFLD RFLA, RFLB RFOUT VDDR AUXOUT PWDNB GNDD XIN VDDD IFLA, IFLB GNDI IFOUT VDDI SENB SCLK SDATA
Description Common ground for RF analog circuitry Pins for inductor connection to RF2 VCO Pins for inductor connection to RF1 VCO Radio frequency (RF) output of the selected RF VCO Supply voltage for the RF analog circuitry Auxiliary output Power down input pin Common ground for digital circuitry Reference frequency amplifier input Supply voltage for digital circuitry Pins for inductor connection to IF VCO Common ground for IF analog circuitry Intermediate frequency (IF) output of the IF VCO Supply voltage for IF analog circuitry Enable serial port input Serial clock input Serial data input
Rev. 1.1
29
S i4 13 3
Table 14. Pin Descriptions for SI4133 Derivatives--MLP
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SI4133 GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR GNDR RFOUT VDDR Si4123 GNDR GNDR GNDR GNDR RFLB RFLA GNDR GNDR GNDR RFOUT VDDR Si4122 GNDR RFLD RFLC GNDR GNDR GNDR GNDR GNDR GNDR RFOUT VDDR Si4113 GNDR RFLD RFLC GNDR RFLB RFLA GNDR GNDR GNDR RFOUT VDDR Si4112 GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD GNDD VDDD
AUXOUT AUXOUT AUXOUT AUXOUT AUXOUT PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDR PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDR PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDR PWDNB GNDD XIN GNDD VDDD GNDD GNDD GNDD GNDD GNDD GNDD VDDD SENB SCLK SDATA GNDR PWDNB GNDD XIN GNDD VDDD GNDD IFLA IFLB GNDI GNDI IFOUT VDDI SENB SCLK SDATA GNDD
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SI4133
Ordering Guide
Ordering Part Number SI4133-BM SI4133-BT Si4123-BM Si4123-BT Si4122-BM Si4122-BT Si4113-BM Si4113-BT Si4112-BM Si4112-BT Description RF1/RF2/IF OUT RF1/RF2/IF OUT RF1/IF OUT RF1/IF OUT RF2/IF OUT RF2/IF OUT RF1 OUT RF1 OUT IF OUT IF OUT Operating Temperature -40 to 85oC -40 to 85oC -40 to 85oC -40 to 85oC -40 to 85oC -40 to 85oC -40 to 85oC -40 to 85oC -40 to 85oC -40 to 85oC
SI4133 Derivative Devices
The SI4133 performs both IF and dual-band RF frequency synthesis. The Si4112, Si4113, Si4122, and the Si4123 are derivatives of this device. Table 15 outlines which synthesizers each derivative device features as well as which pins and registers coincide with each synthesizer.
Table 15. SI4133 Derivatives
Name Si4112 Si4113 Si4122 Si4123 SI4133 Synthesizer IF RF1, RF2 RF2, IF RF1, IF RF1, RF2, IF Pins IFLA, IFLB RFLA, RFLB, RFLC, RFLD RFLC, RFLD, IFLA, IFLB RFLA, RFLB, IFLA, IFLB RFLA, RFLB, RFLC, RFLD, IFLA, IFLB Registers NIF, RIF, PDIB, IFDIV, LPWR, AUTOPDB = 0, PDRB = 0 NRF1, NRF2, RRF1, RRF2, PDRB, AUTOPDB = 0, PDIB = 0 NRF2, RRF2, PDRB, NIF, RIF, PDIB, IFDIV, LPWR NRF1, RRF1, PDRB, NIF, RIF, PDIB, IFDIV, LPWR NRF1, NRF2, RRF1, RRF2, PDRB, NIF, RIF, PDIB, IFDIV, LPWR
Rev. 1.1
31
S i4 13 3
Package Outline: SI4133-BT
2
S R1
E1
E
R
1
L L1
e
3
D
A2
A
c
b A1
Figure 19. 24-pin Thin Small Shrink Outline Package (TSSOP)
Table 16. Package Diagram Dimensions
Symbol A A1 A2 b c D e E E1 L L1 R R1 S 1 2 3 Min -- 0.05 0.80 0.19 0.09 7.70 Millimeters Nom 1.10 -- 1.00 -- -- 7.80 0.65 BSC 6.40 BSC 4.40 0.60 1.00 REF -- -- -- -- 12 REF 12 REF Max 1.20 0.15 1.05 0.30 0.20 7.90
4.30 0.45 0.09 0.09 0.20 0
4.50 0.75 -- -- -- 8
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Rev. 1.1
SI4133
Package Outline: SI4133-BM
Figure 20. 28-Pin Micro Leadframe Package (MLP) Table 17. Package Dimensions
Controlling Dimension: mm Symbol Min A A1 b D D1 E E1 N Nd Ne e L 0.50 -- 0.00 0.18 Millimeters Nom 0.90 0.01 0.23 5.00 BSC 4.75 BSC 5.00 BSC 4.75 BSC 28 7 7 0.50 BSC 0.60 0.75
12
Max 1.00 0.05 0.30
Rev. 1.1
33
S i4 13 3
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free: 1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Rev. 1.1

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